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  1. Paper on GCN inference at ASAP ’20
    Our paper “Accelerate large scale GCN inference on FPGA” has been accepted at the The 31st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP ’20). This paper presents an algorithm-architecture co-optimization framework to accelerate large scale graph convolutional neural network (GCN) inference on FPGA.
  2. FASTHash accepted at ISC '20
    Our paper "FASTHash: FPGA-based High Throughput Parallel Hash Table" has been accepted as a full paper at the ISC High-Performance Conference (ISC 2020). This paper describes a high-throughput parallel hash table architecture for AI applications on FPGA.
  3. Paper on PPO acceleration at FCCM '20
    Our paper "Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms" has been accepted as a full paper at the 28th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM ‘20). This paper describes a high-throughput architectural design for the Deep Reinforcement Learning algorithm -- PPO acceleration on CPU-FPGA heterogeneous platform.
  4. Framework on GCN inference at FCCM ’20
    Our paper “Accelerate large scale GCN inference on FPGA” has been accepted as a poster at the The 28th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM ‘20). This paper presents an algorithm-architecture co-optimization framework to accelerate large scale graph convolutional neural network (GCN) inference on FPGA.
  5. EE 599 offered during Spring 2020
    Recently, Field Programmable Gate Arrays(FPGAs) have become a key computing platform to accelerate applications at data center, cloud, and at the “edge”. This course reviews the technology and software tools from the application acceleration perspective and discusses (application-specific) architectural, software, and algorithmic innovations to realize the potential of this technology to optimize latency, throughput, and…
  6. GraphACT accepted at FPGA '20
    Our paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms" has been accepted as a full paper at the 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '20). This paper describes a novel accelerator design for training GCNs on CPU-FPGA heterogeneous systems by incorporating multiple algorithm architecture co-optimizations.
  7. Paper on CNN acceleration at FPGA '20
    Our paper "Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration" has been accepted as a full paper at the 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '20). It describes a principle designing an approach for low-latency, low-bandwidth, spectral sparse CNN accelerator on FPGAs to overcome the performance gap between…
  8. Angelos Defends his PhD Dissertation
    Ph.D. Candidate Angelos Lazaris successfully defended his Ph.D. Dissertation titled Machine Learning for Efficient Network Management. The defense committee consisted of Professor Viktor K. Prasanna (Chair), Professor Cauligi Raghavendra, and Professor Jyotirmoy V. Deshmukh.
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