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    • Oct. 2024: Soumya Mahapatra will present a multiphase subharmonic switching PA scheme for the first time at ISSCC 2025. This approach enables record high efficiency and EVM among state-of-the-art high data rate (>Gbps) CMOS PA/TX. Congrats Soumya, Mostafa, Ce, Mayank, Shiyu, and Aoyang!
    • Oct. 2024: Ce Yang will present a VCO-based non-uniform multi-level time-approximation filtering scheme for the first time at ISSCC 2025. This approach elevates a TAF receiver to a new level in terms of blocker rejection and implementation cost. Congrats, Ce, Mostafa, Soumya, Maysara, Shiyu and Vinay!
    • Dec. 2023: Juzheng Liu will receive SSCS Pre-doctoral award at ISSCC 2024. Congrats, Juzheng~
    • Oct. 2023: Mostafa Ayesh will present a non-uniform discrete-time FIR filtering scheme for the first time at ISSCC 2024. This approach creates a new direction for a non-uniform sub-sampling receiver that can be used for RF and mm-Wave Communications. Congrats, Mostafa, Soumya, Ce!
    • Feb. 2023: Juzheng Liu received ISSCC Jack Kilby Award at ISSCC 2023 award ceremony! This prestigious award recognizes the delay-tracking pipelined SAR TDC idea and the record energy/area efficiency of the proof-of-concept prototype. Congrats, Juzheng, Mohsen!
    • Oct. 2022: Qiaochu Zhang will present a fractional-N digital MDLL featuring DTC equalizer and injection scrambling technique at ISSCC 2023. The proposed techniques achieve significant spur reduction with limited overhead. Congrats, Qiaochu, Hsiang-chun, Shiyu!
    • Jan. 2023: Qiaochu Zhang received 2022-23 IEEE SSCS predoctoral achievement award and will be recognized at ISSCC and SSCS magazine. Congrats, Qiaochu!
    • June 2022: Ce Yang and Shiyu Su received Best Student Paper Award (First Place) from RFIC 2022. This paper presents a non-uniform time-approximation filter (NU TAF) concept for a receiver frontend. It hints a new direction of analog filtering for future radio design. Congrats, Ce, Shiyu!
    • Oct. 2021: Juzheng Liu will present an 8-bit 10-GS/s ADC featuring a delay-tracking pipelined-SAR TDC at ISSCC 2022. The proposed ADC architecture in 14nm CMOS demonstrates higher power and area efficiency among high-speed (beyond GS/s) ADCs. Congrats, Juzheng, Mohsen!
    • Oct 2021: Qiaochu Zhang received MHI Scholar, a recognition for his PhD works at USC. Congrats, Qiaochu!
    • Sep 2021: Shiyu Su will present a machine-learning based analog mixed-signal circuit generator for time-approximation filter, called TAFA, at ASP-DAC 2022. Congrats, Shiyu, Qiaochu, Juzheng, Mohsen, Rezwan!
    • May 2021: Juzheng Liu will present a machine-learning based analog mixed-signal circuit design flow using transfer learned models from silicon measurement at ICCAD 2021. The automatic layout tool is provided by UMN and Texas A&M. Congrats, Juzheng, Shiyu, Mohsen, Sam, Qiaochu, Rezwan!
    • Feb 2021: Mohsen Hassanpourghadi will present a circuit-connectivity-based neural network structure for analog mixed-signal circuit modeling at DAC 2021. Congrats, Mohsen, Shiyu, Rezwan, Juzheng, and Qiaochu!
    • Jan 2021: Aoyang Zhang will present an SHS PA in mm-Wave band at CICC 2021. Congrats, Aoyang, Mostafa, and Soumya!
    • Jan 2021: Rezwan Rasul will present an in-memory computing chip leveraging passive gain from embedded MOS cap array at CICC 2021. It achieves high energy efficiency for machine learning application. Congrats, Rezwan!
    • Dec 2020: Aoyang Zhang received 2020-21 IEEE SSCS predoctoral achievement award and will be recognized at ISSCC and SSCS magazine. Congrats, Aoyang!
    • Oct 2020: Aoyang Zhang will present the first current-mode SHS PA at ISSCC 2021. This proves SHS PA architecture can be deployed in both voltage and current modes. Congrats, Aoyang, Ce, and Mostafa!
    • Oct 2020: Qiaochu Zhang will present a background two-point DTC calibration scheme for precise injection locking in MDLL at ISSCC 2021. Congrats, Qiaochu, Shiyu, and Cheng-Ru!
    • Oct 2020: Aoyang Zhang receive MHI Scholar at USC in recognition of his PhD works. Congrats, Aoyang!
    • July 2020: Juzheng Liu will present a machine-learning based analog circuit modeling technique (BOAS and TL) at ICCAD 2020. Congrats, Juzheng, Mohsen, Qiaochu, and Shiyu!
    • July 2020: Qiaochu Zhang will present a CNN based early performance assertion scheme (CEPA) at ICCAD 2020. Congrats, Qiaochu, Shiyu, and Juzheng!
    • June 2020: Ce Yang will present the first non-uniform sub-sampling frontend at RFIC 2020. Congrats, Ce, Mostafa, Aoyang, and Tzu-Fan!
    • Dec 2019: Tzu-Fan Wu receives SSCS Predoctoral Achievement Award and will be recognized during ISSCC 2020. Congrats, Tzu-Fan!
    • Oct 2019: Tzu-Fan Wu will present a world first VCO-based non-uniform sampling ADC with fully integrated non-uniform DSP at ISSCC 2020.  It hints new opportunities in future ADC design based on non-uniform sampling concept. Congrats, Tzu-Fan!
    • Oct 2019: Shiyu Su will present an RF transmitter based on tri-level time-approximation filter (TAF) at ISSCC 2020. The tri-level TAF enables record low OOB noise floor without using a SAW filter. Congrats, Shiyu!
    • Oct 2019: Shiyu Su received MHI Scholar, a recognition for his PhD works at USC. Congrats, Shiyu!
    • April 2019: Jaewon Nam received the Best Student Paper Award at CICC 2019 Congrats, Jaewon!
    • April 2019: Shiyu Su will present a time approximation filter technique for a RF transmitter at VLSI Symposium 2019. The technique provides a new direction for RF filtering with low cost. Congrats, Shiyu!
    • Feb 2019: Jaewon Nam will present a mixed-signal equalization for ADC-based wireline receiver at CICC 2019. Congrats, Jaewon!
    • Feb 2019: Mohsen Hassanpourghadi will present a time-based ADC architecture with passive pulse-shrinking technique at CICC 2019. Congrats, Mohsen!
    • Nov 2018: Aoyang Zhang receives Best Poster Award at 9th Annual EE Research Festival in USC EE department. Congrats, Aoyang!
    • Nov 2018: Aoyang Zhang will present a Watt-level SHS PA at ISSCC 2019. Congrats, Aoyang!
    • June 2018: Aoyang Zhang presents a sub-harmonic switching PA architecture at VLSI Symposium. The technique shows superior power backoff efficiency. Congrats, Aoyang!
    • Dec 2017: Shiyu Su receives Predoctoral Achievement Award from IEEE Solid-State Circuits Society. Congrats, Shiyu!
    • Nov 2017: Tzu-Fan Wu receives Best Poster Award at 8th Annual EE Research Festival among 80 poster presenters from USC EE department. Congrats, Tzu Fan!
    • Nov 2017: Cheng-Ru Ho will present a dither-assisted pulling mitigation at ISSCC 2018 for mitigating the interference coupling from both DCO and reference Path simultaneously for the first time. Congrats, Cheng Ru!
    • Nov 2017: Shiyu Su will present a flexible bandpass hybrid DAC architecture at ISSCC 2018 for synthesizing high-fidelity signal within DC to 6GHz tunable passbands.  Congrats, Shiyu!
    • Dec 2017: Shiyu Su receives Predoctoral Achievement Award from IEEE Solid-State Circuits Society. Congrats, Shiyu!
    • Nov 2017: Shiyu Su will present a flexible bandpass hybrid DAC architecture at ISSCC 2018 for synthesizing high-fidelity signal within DC to 6GHz tunable passbands.  Congrats, Shiyu!

    • Nov 2017: Cheng-Ru Ho will present a background dither noise cancellation loop at ISSCC 2018 for mitigating near carrier fractional spurs. Congrats, Cheng Ru!

    • June 2017: Rezwan Rasul will present a Time multiplexed architecture for large-scale neuromorphic computing at MWSCAS 2017. Congrats, Rezwan and Pedram!

    • Dec 2016: Cheng-Ru Ho receives Predoctoral Achievement Award from IEEE Solid-State Circuits Society. Congrats, Cheng Ru!

    • June 2016:Cheng-Ru Ho will present a DCO Spur mitigation scheme at ESSCIRC 2016. Congrats, Cheng Ru!

    • Mar 2016:Jaewon Nam will present a 12-b 1.6GS/s dual reference multi-bit SAR architecture at VLSI 2016. This ADC achieves record  ENOB and power efficiency for GHz signal bandwidth compared to previously published ADCs.  Congrats, Jaewon, Aoyang and Mohsen!

    • Nov 2015:Cheng Ru Ho will present a new fractional-N digital PLL architecture with feedforward multi-tone cancellation at ISSCC 2016. This PLL achieves new record low reference spur (<-110dBc) and in-band fractional spurs (<-73dBc) compared to any published analog or digital PLL.  This work provides new design direction for future PLLs, beyond what existing PLLs can do. Congrats, Cheng Ru!

    • Nov 2015:Shiyu Su will present a new timing and noise cancellation scheme for dual-rate hybrid DAC (with 1GHz bandwidth) at ISSCC 2016. This DAC achieves new record SFDR and IM3 compared to any high-speed CMOS DAC.  Congrats, Shiyu!

    • Step 2015: Tzu Fan Wu presented the first Flash-based Non-Uniform Sampling ADC architecture at CICC 2015. This ADC architecture provides new opportunity to perform anti-aliasing filtering in the digital domain. Congrats, Tzu Fan and the team!

    • Aug 2014:Dr. Chen recently gives a tutorial on “Asynchronous SAR ADC: Past, Present and Beyond”. The slides can be downloaded here [pdf].

    • March 2014:Shiyu Su will present the first hybrid DAC architecture with delta-sigma assisted pre-distortion technique at VLSI Symposium 2014. This DAC achieves the new record linearity among all published high-speed (>GS/s) CMOS DACs (up to date). Congrats, Shiyu and the team!

    • Feb 2014:Cheng-Ru Ho will present the first digital PLL architecture with adaptive spur cancellation technique and low-cost time-to-digital conversion at RFIC 2014. It achieves unprecedented spur rejection by >40dB (measured data).Congrats, Cheng Ru!

    • July 2013:Jaewon Nam will present a new asynchronous SAR ADC architecture with passive gain stage at CICC Sep, 2013, achieving the best Figure-of-Merit (J/conv-step) in its class (up to date) .  Congrats, Jaewon!

    • July 2013:Praveen Sharma will present a new Nyquist VCO-based ADC architecture at CICC Sep, 2013. It achieves >400MHz bandwidth for the first time among published VCO-based ADC. Congrats, Praveen!

    • Dec. 2012:Dylan Hand presented a new non-uniform ADC architecture at Globecom Dec. 2012. Congrats, Dylan!

University of Southern California