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Goal

Our research goal is to explore the optimal analog circuit and system architecture with diminishing power and area consumption in the future nano-scale technologies.  In many cases, we aim at reshaping the analog and digital boundary of the circuit/system architecture, and leveraging what technology scaling offers to address the future analog design challenges.

At the circuit level, we are interested in pushing the boundary of various critical analog mixed-signal, RF components, such as data converters (ADC, DAC), power amplifier (PA), phase locked loop (PLL) frequency synthesizer, etc.  At the system level, we are also interested in wireless/wireline communication systems and emerging applications, such as bio-related, sensing systems, computing platform (machine learning/artificial intelligence/neural network).

Our current research activities generally span over the following areas: (1) data converter, (2) wireless, (3) wireline, (4) computing, and (5) design methodology.

 

Key Group Contributions

  • Asynchronous SAR ADC (since 2006)
  • Embedded TDC scheme for DPLL (since 2010)
  • Non-uniform sampling ADC with digital anti-aliasing filter (since 2012)
  • Direct spur/pulling cancellation for DPLL (since 2014)
  • Dual-rate hybrid DAC (since 2014) 
  • Dual reference shifting SAR ADC (since 2016)
  • Sub-harmonic switching PA (since 2018)

 

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