Our paper “FPGA Acceleration of Number Theoretic Transform” has been accepted at the ISC High-Performance Conference 2021 (ISC’21). This paper proposed a novel low latency fully pipelined modular arithmetic logic to implement the NTT core.
Led by Dr. Viktor K. Prasanna
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Our paper “FPGA Acceleration of Number Theoretic Transform” has been accepted at the ISC High-Performance Conference 2021 (ISC’21). This paper proposed a novel low latency fully pipelined modular arithmetic logic to implement the NTT core.
