Designers:
Juzheng Liu, Mohsen Hassanpourghadi
Tapeout:
GF 14nm, September 2021
Description:
A Time-domain ADC with Delay-tracking Pipelined-SAR TDC
Designers:
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho
Tapeout:
TSMC 65nm, March 2020
Description:
A Fractional-N Digital MDLL with Two-Point DTC Calibration
Designers:
Shiyu Su
Tapeout:
TSMC 65nm, May 2019
Description:
A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation
Designers:
Tzu-Fan Wu
Tapeout:
TSMC 65nm, May 2019
Description:
A 40MHz-BW 76.2dB/78.0dB SNDR/DR noise-shaping nonuniform sampling ADC with single phase-domain level crossing and embedded nonuniform digital signal processor in 28nm CMOS
Designers:
Ce Yang
Tapeout:
TSMC 28nm, May 2019
Description:
A 29-mW 26.88-GHz Non-Uniform Sub-Sampling Receiver Front-End Enabling Spectral Alias Spreading and > 30dB Alias Rejection
Designers:
Shiyu Su
Tapeout:
TSMC 65nm, June 2018
Description:
A 1-5GHz DDRM with Time-Approximation Filter achieving -158dBc/Hz OOB NSD and -43dB EVM at 1024 QAM
Designers:
Aoyang Zhang
Tapeout:
TSMC 65nm, June 2018
Description:
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency
Designers:
Jae-Won Nam
Tapeout:
TSMC 65nm, April 2018
Description:
A 12.8 Gbaud/s Wireline RX
Designers:
Mohsen Hassanpourghadi
Tapeout:
TSMC 65nm, April 2018
Description:
A 7.3-bit 10GS/s Time Based Passive Pulse Shrinking ADC
Designers:
Aoyang Zhang
Tapeout:
TSMC 65nm, June 2017
Description:
A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency
Designers:
Tzu-Fan Wu
Tapeout:
TSMC 65nm, June 2017
Description:
Voltage-Controlled-Oscillator-Based Nonuniform Sampling ADC
Designers:
Shiyu Su
Tapeout:
TSMC 65nm, May 2017
Description:
A 16b 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC-to-6GHz Tunable Passbands
Designers:
Cheng-Ru Ho
Tapeout:
TSMC 65nm, May 2017
Description:
A Digital Frequency Synthesizer with Dither-assisted Pulling Mitigation Scheme
Designers:
Cheng-Ru Ho
Tapeout:
TSMC 65nm, May 2017
Description:
A Fractional-N PLL with Background Dither Noise Cancellation for Near-carrier Fractional-spur Cancellation
Designers:
Shiyu Su
Tapeout:
TSMC 65nm, May 2016
Description:
A 12b 2GS/s Dual-rate Hybrid DAC with Pulsed Timing Error Pre-distortion and In-band Noise Cancellation Achieving >74dBc SFDR up to 1GHz
Designers:
Tzu-Fan Wu
Tapeout:
TSMC 65nm CMOS, June 2015
Description:
Subranging-Based Nonuniform Sampling ADC
Designers:
Cheng-Ru Ho
Tapeout:
TSMC 65nm CMOS, May 2015
Description:
A Fractional-N PLL with Feedforward Multi-tone Spur Cancellation Scheme
Designers:
Cheng-Ru Ho
Tapeout:
TSMC 65nm CMOS, May 2015
Description:
A Fractional-N PLL with DCO-induced Spur Cancellation Scheme
Designers:
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang
Tapeout:
TSMC 65nm, Feb 2015
Description:
A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-interleaved SAR ADC with Dual Reference Shifting and Interpolation
Designers:
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma
Tapeout:
TSMC 65nm, June 2014
Description:
A 12-bit Hybrid DAC with 8GS/s Unrolled Pipeline Delta-Sigma Modulator achieving >75dB SFDR over 500MHz
Designers:
Tzu-Fan Wu, Cheng-Ru Ho
Tapeout:
TSMC 65nm CMOS, June 2013
Description:
Flash-Based Nonuniform Sampling ADC
Designers:
Cheng-Ru Ho
Tapeout:
TSMC 65nm CMOS, May 2013
Description:
A Fractional-N PLL with Adaptive Single-Tone Spur Cancellation Scheme and Injection-Locked Time-to-digital Converter
Designers:
Jae-Won Nam, David Chiong
Tapeout:
TSMC 65nm, Feb 2012
Description:
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB, 1.36-mW at 95-MS/s in 65nm CMOS