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Publications

Conferences

  • S. Mahapatra, M. Ayesh, C. Yang, M. Palaria, S. Su, A. Zhang, M. S.-W. Chen, “A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gbps Data Rate and -30.8dB EVM in 65nm CMOS“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025. (to be presented)
  • C. Yang, S. Su, M. Ayesh, S. Mahapatra, M. Hamada, V. Chenna, H. Hashemi, M. S.-W. Chen, “A Blocker Tolerant Receiver with VCO-based Non-Uniform Multi-Level Time-Approximation Filter With -36dB EVM in 28nm CMOS“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025. (to be presented)
  • J. Liu, A. Shabra, S. Ho, G. Manganaro, M. S.-W. Chen, “A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS” in IEEE Symposium on VLSI Technology and Circuits (VLSI Technol. Circuits), June 2024.
  • Q. Zhang*, S. Su*, B. R. Biswas, S. Gupta, M. S.-W. Chen, “Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder With 0.012mm2 Active Area in 12nm FinFET,” in IEEE Symposium on VLSI Technology and Circuits (VLSI Technol. Circuits), June 2024. (* equal contribution)
  • Q. Zhang*, S. Su*, Z. Liu*, H.-C. Cheng, Z. Qiu, M. Palaria, J. Ye, D. Meng, B. Chen, S. Hossain, W. Wu, M. S.-W. Chen, “A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems,” in IEEE Symposium on VLSI Technology and Circuits (VLSI Technol. Circuits), June 2024. (* equal contribution) (to be presented)
  • M. Ayesh, S. Mahapatra, C. Yang and M. S.-W. Chen, “A 0.072-mm2 18-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
  • M. Palaria, S. Su, H.-C. Cheng, R. Rasul, Q. Zhang, S. Mahapatra, C.-F. Law, S. Hossain, R. Bena, W. Wu, Q. Nguyen, M. S.-W. Chen, “Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS“, in IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2023.
  • H.-C. Cheng, S. Su, M. Palaria, Q. Zhang, C. Yang, S. Hossain, R. Bena, B. Chen, Z. Liu, J. Liu, R. Rasul, Q. Nguyen, W. Wu, M. S.-W. Chen, “A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems,” in IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023. Download Link
  • S. Su*, Q. Zhang*, and M. S.-W. Chen, “A 2GS/s 8.5-Bit Time-Based ADC Using a Segmented Stochastic Flash TDC,” in IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023 (* equal contribution) Download Link
  • Q. Zhang, H.-C. Cheng, S. Su, and M. S.-W. Chen, “A Fractional-N Digital MDLL with Injection Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. Download Link
  • Q. Zhang*, S. Su*, and M. S.-W. Chen, “A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling,” in 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC), July 2022. ( *contributed equally to this work) Download Link
  • C. Yang, S. Su and Mike Chen, “A Millimeter-Wave Mixer-First Receiver with Non-Uniform Time-Approximation Filter Achieving >45-dB Blocker Rejection,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2022. (Best Student Paper Award – First Place) Download Link
  • S. Su and M. S.-W. Chen, “High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range,” (Invited) IEEE Custom Integrated Circuits Conference (CICC), April 2022. (Best Invited paper candidate) Download Link
  • S. Su, Q. Zhang, M. Hassanpourghadi, J. Liu, R.A. Rasul, and M. S.-W. Chen, “AMS Circuit Synthesis Enabled by the Advancements of Circuit Architectures and ML Algorithms,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022. Download Link
  • J. Liu, M. Hassanpourghadi, and M. S.-W. Chen, “A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.
  • S. Su, Q. Zhang, J. Liu, M. Hassanpourghadi, R.A. Rasul, and M. S.-W. Chen, “TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture,” in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022. Download Link
  • J. Liu, S. Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A. Kumar, S. S. Sapatnekar, R. Harjani, A. Levi, S. Gupta and M. S.-W. Chen, “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning“, 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2021. Download Link
  • M. Hassanpourghadi, S. Su, R.A. Rasul, J. Liu, Q. Zhang, and M. S.-W. Chen, “Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling,” 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC), Dec. 2021. Download Link
  • R.A. Rasul, and M. S.-W. Chen, “A 128×128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021.
  • A. Zhang, M. Ayesh, S. Mahapatra, and M. S.-W. Chen, “A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2,2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2021.
  • Q. Zhang, S. Su, C.-R. Ho, and M. S.-W. Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. Download Link
  • A. Zhang, C. Yang, M. Ayesh, and M. S.-W. Chen, “A 5-to-6 GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-off Efficiency,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.
  • Q. Zhang, S. Su, J. Liu, and M. S.-W. Chen, “CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020. Download Link
  • J. Liu, M. Hassanpourghadi, Q. Zhang, S. Su, and M.S.-W. Chen, “Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling,” in 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2020.
  • C. Yang, M. Ayesh, A. Zhang, T.-F. Wu and M. S.-W. Chen, “A 29-mW 26.88-GHz Non-Uniform Sub-Sampling Receiver Front-End Enabling Spectral Alias Spreading,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2020.
  • S. Su and M. S.-W. Chen, “A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. Download Link
  • T.-F. Wu and M. S.-W. Chen, “A 40MHz-BW 76.2dB/78.0dB SNDR/DR noise-shaping nonuniform sampling ADC with single phase-domain level crossing and embedded nonuniform digital signal processor in 28nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
  • S. Su, M.S.-W. Chen, “A 1–5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM,” IEEE Symposium on VLSI Circuits (VLSIC), June 2019. Download Link
  • J.W. Nam, M.S.-W. Chen, “A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), April 2019.
  • M. Hassanpourghadi, M.S-W Chen, “A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells,” IEEE Custom Integrated Circuits Conference (CICC), April 2019.
  • A. Zhang and M. S.-W. Chen, “A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.
  • A. Zhang, M. S.-W. Chen, “A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency,“ IEEE Symposium on VLSI Circuits (VLSIC), June 2018.
  • T.F. Wu, M. S.-W. Chen, “A 200MHz-BW 0.13mm2 62dB-DR VCO-Based Non-Uniform Sampling ADC with Phase-Domain Level Crossing in 65nm CMOS,“ IEEE Custom Integrated Circuits Conference (CICC), April 2018.
  • S. Su and M. S.-W. Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018. Download Link
  • C.R. Ho, M. S.-W. Chen, “A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
  • C.R. Ho, M. S.-W. Chen, “A fractional-N digital PLL with background dither noise cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spur in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
  • R. Rasul, P. Teimouri, and M. S.-W. Chen, “A Time Multiplexed Network Architecture for Large-Scale Neuromorphic Computing,” IEEE MWSCAS, August 2017.
  • C.R. Ho, M. S.-W. Chen, “Interference-Induced DCO Spur Mitigation for Digital Phase Locked Loop in 65-nm CMOS,” IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2016.
  • J.W. Nam, M. Hassanpourghadi, A. Zhang, and M.S.-W. Chen, “A 12-bit 1.6 GS/s Interleaved SAR ADC with Dual Reference Shifting and Interpolation Achieving 17.8 fJ/conv-step in 65nm CMOS,” IEEE Symposium on VLSI Circuits (VLSIC), June 2016.
  • C.R. Ho, M. S-W Chen, “A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016.
  • S. Su, M. S-W. Chen, “A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016. Download Link
  • T.F. Wu, C.R. Ho, M. Chen, “A Flash-Based Non-Uniform Sampling ADC Enabling Digital Anti-Aliasing Filter in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Sep 2015.
  • S. Su, T. Tsai, P. Sharma, M. S.W. Chen, “A 12-bit Hybrid DAC with 8GS/s Unrolled Pipeline Delta-Sigma Modulator achieving >75dB SFDR over 500MHz in 65nm CMOS,” IEEE Symposium on VLSI Circuits (VLSIC), June 2014. Download Link
  • C.R. Ho, M. S.W. Chen, “A Fractional-N DPLL with Adaptive Spur Cancellation and Calibration-Free Injection-Locked TDC in 65nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June, 2014.
  • J.W. Nam, D. Chiong, and M. S.W. Chen, “A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013
  • P.K. Sharma, and M. S.W. Chen, “A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO Based ADC in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013
  • M. S.W. Chen, “ Trend of High-Speed SAR ADC towards RF Sampling,” 10th International Conference on Sampling Theory & Applications (SampTA) (Invited), July. 2013.
  • D. Hand, and M. S.W. Chen, “A Non-Uniform Sampling ADC Architecture with Embedded Alias-Free Asynchronous Filter,” Global Telecommunications Conference (GLOBECOM), Dec. 2012.
  • M. S.W. Chen, “Overhead Minimization Techniques for Digital Phase-Locked Loop Frequency Synthesizer, “ IEEE MWSCAS (Invited Session), Aug. 2012.
  • M.S.W. Chen, D. Su, S. Mehta, “A Calibration-Free 800MHz Fractional-N Digital PLL with Embedded TDC,” IEEE International Solid-State Circuits Conference (ISSCC),Feb. 2010.
  • Nathawad, L.; Zargari, M.; Samavati, H.; Mehta, S.; Kheirkhahi, A.; Chen, P.; Gong, K.; Vakili-Amini, B.; Hwang, J.; Chen, M.S.W.; Terrovitis, M.; Kaczynski, B.; Limotyrakis, S.; Mack, M.; Gan, H.; Lee, M.; Abdollahi-Alibeik, S.; Baytekin, B.; Onodera, K.; Mendis, S.; Chang, A.; Jen, S.; Su, D.; Wooley, B., “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” IEEE International Solid-State Circuits Conference (ISSCC),Feb. 2008.
  • A. Fort, M.S.W. Chen, R.W. Brodersen, C. Desset, P. Wambacq, L. Van Biesen, “Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications,” IEEE International Conference on Communications (ICC), June 2007.
  • A. Fort, M.S.W. Chen, C. Desset, P. Wambacq, L. Van Biesen, “Clock offset tracking for subsampling UWB architectures in a body area network,” IEEE International Conference on Ultra-Wideband (ICUWB), Sep. 2007.
  • M.S.W. Chen and R. W. Brodersen, “Digital Complex Signal Processing Techniques for Impulse Radio,” Global Telecommunications Conference (GLOBECOM), Nov. 2006.
  • M.S.W. Chen and R. W. Brodersen, “Implementation Considerations for a Sub-sampling Impulse Radio,” IEEE International Conference on Ultra-Wideband (ICUWB), Sep. 2006.
  • M.S.W. Chen and R. W. Brodersen, “A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2006.
  • D. Cabric, M.S.W. Chen, D. Sobel, J. Yang, and R. Brodersen, “Future Wireless Systems: UWB, 60 GHz, and Cognitive Radios,” (Invited paper) at Custom Integrated Circuits Conference (CICC), Sep. 2005
  • M.S.W. Chen, R. W. Brodersen, “The Impact of a Wideband Channel on UWB System Design,” Military Communication Conference (MILCOM), Nov. 2004.
  • M.S.W. Chen, R. W. Brodersen, “A Subsampling UWB Radio Architecture by Analytic Signaling,” International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2004.
  • I. O’Donnell, M. Chen, S. Wang, R. W. Brodersen, “An Integrated, Low-Power, Ultra-Wideband Transceiver Architecture for Low-Rate, Indoor Wireless Systems,” IEEE CAS Workshop on Wireless Communications and Networking, Sep. 2002.

Journals

  • M. Ayesh, S. Mahapatra, C. Yang and M. S.-W. Chen, “A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter“, IEEE J. Solid-State Circuits, 2024. (In-press)
  • Q. Zhang, H.-C. Cheng, S. Su, and M. S.-W. Chen, “Fractional-N Digital MDLL with Injection-Error Scrambling and Calibration,” IEEE J. Solid-State Circuits, 2023. Download Link
  • C. Yang, S. Su, and M. S.-W. Chen, “Millimeter-Wave Receiver with Non-Uniform Time-Approximation Filter,” IEEE J. Solid-State Circuits, 2023. Download Link
  • J. Liu, M. ‪Hassanpourghadi‬, and M. S.-W. Chen, “A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC,” IEEE J. Solid-State Circuits, 2022.
  • S. Su, and M. S.-W. Chen, “SAW-Less Direct RF Transmitter with Multi-Mode Noise Shaping and Tri-Level Time-Approximation Filter,” IEEE J. Solid-State Circuits, 2022. Download Link
  • Q. Zhang, S. Su, C.-R. Ho, and M. S.-W. Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration,” IEEE J. Solid-State Circuits (JSSC), vol. 57, no. 1, Jan. 2022. (Invited Paper) Download Link
  • X. Yan, J. Ma, T. Wu, A. Zhang, J. -B. Wu, M. Chin, Z. Zhang, M. Dubey, W. Wu, M. S.-W. Chen, J. Guo, H. Wang “Reconfigurable Stochastic Neurons Based on Tin Oxide/MoS2 Hetero-memristors for Simulated Annealing and the Boltzmann Machine” Nature Communications, 12, Article number: 5710 (2021)
  • S. Su and M. S.-W. Chen, “A Time-Approximation Filter for Direct RF Transmitter,” IEEE J. Solid-State Circuits (JSSC), 2021 (early access). Download Link
  • J.W. Nam, M. S-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” (Invited) IEEE J. Solid-State Circuits (JSSC), 2020. Download Link
  • A. Zhang, M. S-W. Chen, “A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier,” (Invited) IEEE J. Solid-State Circuits (JSSC) Nov., 2019.
  • A. Zhang, M. S-W. Chen, “A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement,” (Invited) IEEE J. Solid-State Circuits (JSSC) Feb., 2019.
  • T.-F. Wu and M. S.-W. Chen, “A noise-shaped VCO-based nonuniform sampling ADC with phase-domain level crossing,” IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 3, Mar. 2019. (Invited Paper)
  • S. Su, M. S-W. Chen, “A 16-bit 12GS/s Single/Dual-Rate DAC with a Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 within DC to 6GHz Tunable Passbands,” (Invited) IEEE J. Solid-State Circuits (JSSC) Dec., 2018. Download Link
  • T.F. Wu, M. S-W. Chen, “A Subranging-Based Nonuniform Sampling ADC With Sampling Event Filtering,” IEEE Solid-State Circuits Letters (SSC-L) April, 2018.
  • J.W. Nam, M. Hassanpourghadi, A. Zhang, M.S-W Chen, “A 12-bit 1.6/3.2/6.4 GS/s 4 b/cycle Time-interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits (JSSC), June, 2018.
  • T.F. Wu, C.R. Ho, M. S.W Chen, “A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter,” IEEE J. Solid-State Circuits (JSSC) Sep., 2017.
  • M. Hassanpourghadi, P.K. Sharma, and M. S.W. Chen, “A 6-bit Nyquist AC-coupled VCO Based ADC at 800MS/s,” IEEE Transactions on Circuits and Systems (TCAS-I) 2017.
  • C.R. Ho, M. S.W. Chen, “A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS,” (Invited) accepted for IEEE J. Solid-State Circuits (JSSC) Dec., 2016.
  • S. Su, M. S-W. Chen, “A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS,” (Invited) IEEE J. Solid-State Circuits (JSSC) Dec., 2016. Download Link
  • J.W. Nam, M. Chen, “An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving >10 ENOB, 1.36 mW at 95MS/s in 65nm CMOS,” IEEE Transactions on Circuits and Systems (TCAS-I) 2016
  • T.F. Wu, S. Dey, M. Chen, “A Non-Uniform Sampling ADC Architecture with Reconfigurable Digital Anti-aliasing Filter,” IEEE Transactions on Circuits and Systems (TCAS-I) 2016
  • C.R. Ho, M. S-W. Chen, “A Fractional-N DPLL with Calibration-free Multi-phase Injection-locked TDC and Adaptive Single-tone Spur Cancellation Scheme,” IEEE Transactions on Circuits and Systems (TCAS-I) 2016
  • S. Su, T. Tsai, P. Sharma, M. S.W. Chen, “A 12-bit 1GS/s Dual-Rate Hybrid DAC with an 8GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving >75dB SFDR over the Nyquist Band,” (Invited) IEEE J. Solid-State Circuits (JSSC), April, 2015. Download Link
  • K. Cao, J. Velamala, K. Sutaria, M. S.W. Chen, J. Ahlbin, I. Esqueda, M. Bajura, M. Fritze, “Cross-Layer Modeling and Simulation of Circuit Reliability”, IEEE Transactions on CAD of Integrated Circuits and Systems, Jan. 2014.
  • M. S.W. Chen, D. Su, S. Mehta, “A Calibration-Free 800MHz Fractional-N Digital PLL with Embedded TDC,” (Invited) IEEE Journal of Solid-State Circuits (JSSC), Dec. 2010.
  • Zargari, M.; Nathawad, L.Y.; Samavati, H.; Mehta, S.S.; Kheirkhahi, A.; Chen, P.; Gong, K.; Vakili-Amini, B.; Hwang, J.A.; Chen, S.-W.M.; Terrovitis, M.; Kaczynski, B.J.; Limotyrakis, S.; Mack, M.P.; Gan, H.; MeeLan Lee; Chang, R.T.; Dogan, H.; Abdollahi-Alibeik, S.; Baytekin, B.; Onodera, K.; Mendis, S.; Chang, A.; Rajavi, Y.; Jen, S.H.-M.; Su, D.K.; Wooley, B.A., “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” IEEE J. Solid-State Circuits (JSSC), Dec. 2008.
  • M. S.W. Chen, R. W. Brodersen, “A Subsampling Radio Architecture for Ultrawideband Communications,” IEEE Transactions on Signal Processing, Oct. 2007.
  • M. S.W. Chen, R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-um CMOS,” IEEE J. Solid-State Circuits (JSSC), Dec. 2006.
  • M. S.W. Chen, R. W. Brodersen, “A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling,” (Invited Paper) IEICE Trans. on Electronics, June 2005.
  • D. Cabric, M.S.W. Chen, D. Sobel, S. Wang, J. Yang, and R. W. Brodersen, “Novel Radio Architectures for UWB, 60GHz, and Cognitive Wireless Systems,” EURASIP J. on Wireless Commnucations and Networking, 2006.

Magazine

  • M. S.-W. Chen, “Trend and New Opportunities in Digital PLL Design”, (Invited) IEEE Solid State Circuit Magazine, 2020 winter issue.
  • C. R Ho, M. S-W. Chen, “Spur and Interference Mitigation Techniques for Digital Phase-Locked Loop Architecture,” IEEE Microwave Magazine 2019 (invited and under review).
  • Sankaran, S.G.; Zargari, M.; Nathawad, L.Y.; Samavati, H.; Mehta, S.S.; Kheirkhahi, A.; Chen, P.; Ke Gong; Vakili-Amini, B.; Hwang, J.; Chen, S.-W.M.; Terrovitis, M.; Kaczynski, B.J.; Limotyrakis, S.; Mack, M.P.; Gan, H.; Lee, M.; Chang, R.T.; Dogan, H.; Abdollahi-Alibeik, S.; Baytekin, B.; Onodera, K.; Mendis, S.; Chang, A.; Rajavi, Y.; Jen, S.H.-M.; Su, D.K.; Wooley, B., “Design and implementation of a CMOS 802.11n soc –[integrated circuits for communications],” Communications Magazine, April 2009.
  • D. Cabric, I. O’Donnell, M.S.W. Chen, and R.W. Brodersen, “Spectrum Sharing Radios,” (Invited) IEEE Circuits and Systems Magazine, 2006.

Book Chapter

  • M. S.W. Chen, “Challenges and Emerging Trend of DSP Enabled Frequency Synthesizer,” Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Chapter4, 2015, Cambridge University Press.
  • M. S.W. Chen, “Energy-Efficient ADC Topology Enabled with Asynchronous Techniques,” Circuits for Nanoscale: Communications, Imaging, and Sensing. Chapter14, Sep. 2008.
University of Southern California