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Hardware Security

The E2S2C group is collaborating with the USC/ISI SURE Center and Professor Pierluigi Nuzzo’s group at USC in the area of evaluating and protecting VLSI designs against a variety of hardware attacks. In particular, given the complex and distributed nature of the VLSI fabrication and packaging industry, attacks occur during a variety of points in the IC supply chain and a chip’s life cycle and can lead to the insertion of hardware Trojans or the counterfeiting of ICs.  Our recent focus has been on logic locked circuits that force users to use a secret key to unlock the circuit and operate it successfully.  Our techniques are based on machine learning, statistical analysis, linear algebra in the Boolean GF(2) space, as well as integer linear programming.

List of group members (Ph.D.s): Dake Chen, Xuan Zhou, Yuke Zhang

List of publications:

  1. [GLSVLSI 2023] D. Chen, C. Goins, M. Waugaman, G. D. Dimou, P. A. Beerel “Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks” (invited paper)
  2. [IEEE Trans on CAD] Hu, Y. Zhang, K. Yang, D. Chen, P. A. Beerel, and P. Nuzzo. “On the Security of Sequential Logic Locking Against Oracle-Guided Attacks,”  March 2023.
  3. [ISQED 2023] D.Chen, X. Zhou, Y. Hu, Y. Zhang, K. Yang, A. Rittenbach, P.  Nuzzo and P. A. Beerel. “Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP.”
  4. [CHES 2022] P. A. Beerel, M. Georgiou, B. Hamlin, A. J. Malozemoff, P. Nuzzo. “Towards a Formal Treatment of Logic Locking”, Conference on Cryptographic Hardware and Embedded Systems.
  5. [DATE 2022] Y. Zhang*, Y. Hu*, P. Nuzzo and P. A. Beerel , “TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks”.
  6. [IEEE DFTS 2021] D. Chen, C. Lin, P. A. Beerel, “GF-Flush: A GF(2) Algebraic Attack on Secure Scan Chains”.
  7. [IEEE HOST 2021] Y. Hu., Y. Zhang, K. Yang, D. Chen, P. A. Beerel, P. Nuzzo, “Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption
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